For example, technologies regarding semiconductor memory devices studied by the inventors include the following technologies.
In a one-transistor one-capacitor DRAM (Dynamic Random Access Memory) typical as a high-density large-capacity semiconductor memory, as shown in FIG. 29A, a transistor M which is turned ON/OFF by the potential of a word line WL and a memory capacitor C are connected in series between a bit line BL and a common potential line (for example, ground potential GND) to form a memory cell. In this memory cell, information is stored by accumulating different amounts of charge into the capacitor C depending on the setting of the potential of the bit line BL in a write operation. In a read operation, the bit line is directly charged and discharged by a signal charge retained in the capacitor C and changes in potential of the bit line are amplified by a sense amplifier, thereby determining whether the storage information indicates “1” or “0”. Therefore, in order to ensure a stable operation at the time of reading the storage information, it is necessary to provide a sufficient capacitance.
However, along with the development of microfabrication of memory cells, the area that can be used for the capacitor is decreased. Therefore, by the further microfabrication of memory cells, an accumulated amount of charge is decreased, and the amplitude of a read signal is reduced. As a result, it becomes impossible to ensure the stable operation at the time of reading. For its prevention, generation after generation, technologies to ensure a certain amount of signal charge such as making the capacitor C more spatial and increasing a dielectric constant of a capacitor insulating film have been developed. However, a novel high dielectric constant material has to be developed for each generation, and the scaling has become more and more difficult.
To solve the problem above, as shown in FIG. 29B, a so-called gain cell has attracted attention, in which a signal charge is retained at the gate electrode of a read transistor M1 and the signal is amplified by the read transistor M1 and then outputted to the bit line BL at the time of reading (for example, FIG. 16 of Japanese Patent Application Laid-Open Publication No. 2001-53167 (Patent Document 1)). Such a gain-cell structure can ensure a sufficient read signal even with a small amount of accumulated charge, and thus, the gain-cell structure is suitable for microfabrication.
FIG. 29B is a circuit diagram depicting a structure example of a two-transistor one-capacitor memory cell, which is one type of gain cell. As shown in FIG. 29B, the memory cell is formed of a write transistor M2, a read transistor M1, and a capacitor C. The write transistor M2 has a gate connected to a word line WL, and one of a source and drain thereof is connected to a bit line BL. The read transistor M1 has a gate connected to the other of the source and drain of the write transistor M2, a source connected to the bit line BL, and a drain connected to a supply line of a reference potential (for example, a ground potential GND). One electrode of the capacitor C is connected to a midpoint of the connection between the read transistor M1 and the write transistor M2, and the other electrode thereof is connected to the word line WL. The one electrode of the capacitor C and the midpoint of the connection between the read transistor M1 and the write transistor M2 connected thereto form a storage node SN of the memory cell.
In another method, a word line is divided into a line for writing and a line for reading, and a read operation is performed while independently controlling the divided word lines. For example, FIG. 2 and the description of Patent Document 1 disclose a technology for a two-transistor one-capacitor DRAM gain cell having a word line for writing and a word line for reading. In a memory cell having such a gain-cell structure, as shown in FIG. 29C, a word line for writing (write word line WWL) and a word line for reading (read word line RWL) are separately provided.